This application claims the priority of Korean Patent Application No. 2003-87251, filed on Dec. 3, 2003, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a memory device employing an inactive weak precharging and equalizing scheme and a precharging method to reduce peak current.
2. Description of the Related Art
The power consumption of a semiconductor memory device is determined by an operating current flowing between a power supply voltage VDD supplied from the outside and a ground voltage VSS. The operating current I produces a predetermined IR drop caused by a resistance component R of a power line through which the power supply voltage VDD is transferred, that is, a voltage drop. In addition, the operating current brings about a predetermined IR rise, i.e., a voltage rise, due to a resistance component R of a power line through which the ground voltage VSS is transferred. This voltage drop or voltage rise on the power line serves as a load when power is provided to a semiconductor memory device.
One method for reducing the power load is to decrease the resistance R of the power line. Specifically, a thick power line is employed for the memory device and this power line is connected in close proximity to a power tab entering the memory device. However, this method reduces a voltage drop occurring inside the memory device but it cannot decrease a voltage drop generated when power is supplied from an external power supply to the memory device. To reduce the voltage drop generated during power supply from the external power supply to the memory device, the operating current I should be decreased.
The second method for reducing the power load is to reduce the operating current I of the memory device. The operating current I corresponds to the sum of instantaneous currents of a plurality of blocks in the memory device. Peak current that causes maximum voltage drop or voltage rise is generated during a precharge cycle of the memory device. This is because large precharge transistors designed to remove the timing loss of the precharge cycle simultaneously operate for each column. This precharge operation is described with reference to FIG. 1.
Referring to FIG. 1, a memory device 100 includes a memory cell block 110, a first precharge block 120, a column selector 130, a second precharge block 140, a precharge driver 150, a write driver 160, and a data input/output circuit 170. Memory cells 111, 112, 113 and 114 connected to wordlines WL0, . . . , WLn are connected to bit lines and complementary bit lines BL0, /BL0, BLm and /BLm. The bit lines and complementary bit lines BL0, /BL0, BLm and /BLm in the memory cell block 110 are selectively connected to the input/output circuit 170 through the column selector 130 so that data of selected memory cells 111, 112, 113 and 114 is inputted and outputted through the data input/output circuit 170.
When the memory cells 111, 112, 113 and 114 are not accessed, transistors 121a-121c, 122a-122c and 140a-140c in the first and second precharge blocks 120 and 140 are turned on in response to the output of the precharge driver 150 that delivers a precharge signal PRECHARGE to precharge the bit lines and complementary bit lines BL0, /BL0, BLm and /BLm. That is, the bit lines and complementary bit lines BL0, /BL0, BLm and /BLm are precharged by the first precharge block 120 located in close proximity to the memory cell block 110 and, at the same time, the bit lines and complementary bit lines BL0, /BL0, BLm and /BLm are precharged by the second precharge block 140 adjoining the data input/output circuit 170 including a sense amplifier (not shown). This rapidly precharges the bit lines and complementary bit lines BL0, /BL0, BLm and /BLm to raise sensing speed. However, this method increases the precharge current, which induces a peak current of the memory device.
A method of reducing the peak current generated during the precharge operation is disclosed in U.S. Pat. No. 6,075,733. Referring to FIG. 2, the circuit construction of U.S. Pat. No. 6,075,733 includes a first precharge circuit 12 for precharging bit lines 16 and 18 and a second precharge circuit 14 for precharging the bit lines 16 and 18 before the first precharge circuit 12 precharges them during a memory operation. The size of transistors 22 of the first precharge circuit 12 is larger than that of transistors 20 of the second precharge circuit 14 (X>Y).
With this circuit construction, the bit lines 16 and 18 are precharged by the second precharge circuit 14 whose drive intensity and current are smaller than those of the first precharge circuit. Then, the bit lines 16 and 18 are finally precharged by the first precharge circuit 12 so as to reduce the peak current. However, this two-step precharging method requires a predetermined period of time for precharging the bit lines 16 and 18.
Accordingly, a precharging method capable of decreasing power consumption while reducing bit line precharge time is needed.